The present invention relates to memory systems, and more specifically, to delay locked loop (DLL) bypass control circuitry for use in a memory system.
As processor speeds continue to increase, memory performance becomes more of a limiting factor in system performance and therefore, memory performance must increase as well. An important aspect of increasing memory performance is increasing the speed at which data can be transmitted between elements (e.g., memory device, memory controller) in the memory system. In a typical memory system, synchronous communication is used to achieve high data transmission rates to and from the memory devices. Memory systems that communicate synchronously use a clock signal as a timing reference so that data can be transmitted and received with a known relationship to this reference. A difficulty in maintaining this relationship is that process, voltage, and temperature variations can alter the timing relationship between the clock and data signals, resulting in reduced timing margins. This problem can get worse as signaling speeds increase and may impact the ability of systems to communicate data at higher speeds.
Clock synchronous circuits such as phase lock loops (PLLs) and DLLs are typically used for maintaining the timing relationship between clock and data signals in a memory system. If the reference (or external) clock signal is different in frequency from an internal clock signal used to drive the data signals, then it is necessary to employ a frequency multiplying function, such as that provided by a PLL circuit. If the external clock signal is equal in frequency to the internal clock signal, then a DLL circuit is typically used to synchronize the internal clock signal used for inputting/outputting the data with the external clock signal.
A drawback to the use of DLLs is that they take a relatively large number of clock cycles to power-up once they have been turned off. This power-up delay time in DLLs contributes to an increased latency in memory access time. To avoid a DLL power-up delay from being added to memory access latency, a DLL may be left running (i.e., powered-on) when a memory device is in a reduced power mode, such as a standby mode. However, when the DLL is left running during standby mode, the DLL consumes a relatively large portion of the power required during memory standby, thus reducing power savings that can be achieved by putting a memory device in a low power mode.
Accordingly, and while existing memory systems may be suitable for their intended purpose, there remains a need in the art for memory systems that overcome these drawbacks.